作者简介:
John L.Hennessy 斯坦福大学校长，IEEE和ACM会士，美国国家工程研究院院士及美国科学艺术研究院院士。Hennessy教授因为在RISC技术方面做出了突出贡献而荣获2001年的Eckert-Mauchly奖章，他也是2001年Seymour Cray计算机工程奖得主，并且和本书另外一位作者David A.Patterson分享了2000年John von Neumann奖。
Computer Architecture
A Quantitative Approach
Third Edition
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Features & Benefits | Description | Contents
John Hennessy
Stanford University
David Patterson
University of California, Berkeley
Features & Benefits
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Presents state-of-the-art design examples including:
IA-64 architecture and its first implementation, the Itanium
Pipeline designs for Pentium III and Pentium IV
The cluster that runs the Google search engine
EMC storage systems and their performance
Sony Playstation 2
Infiniband, a new storage area and system area network
SunFire 6800 multiprocessor server and its processor the UltraSPARC III
Trimedia TM32 media processor and the Transmeta Crusoe processor
Examines quantitative performance analysis in the commercial server market and the embedded market, as well as the traditional desktop market.
Updates all the examples and figures with the most recent benchmarks, such as SPEC 2000.
Expands coverage of instruction sets to include descriptions of digital signal processors, media processors, and multimedia extensions to desktop processors.
Analyzes capacity, cost, and performance of disks over two decades.
Surveys the role of clusters in scientific computing and commercial computing.
Presents a survey, taxonomy, and the benchmarks of errors and failures in computer systems.
Presents detailed descriptions of the design of storage systems and of clusters.
Surveys memory hierarchies in modern microprocessors and the key parameters of modern disks.
Presents a glossary of networking terms.
Description back to top
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This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today. In this edition, the authors bring their trademark method of quantitative analysis not only to high performance desktop machine design, but also to the design of embedded and server systems. They have illustrated their principles with designs from all three of these domains, including examples from consumer electronics, multimedia and web technologies, and high performance computing.
The book retains its highly rated features: Fallacies and Pitfalls, which share the hard-won lessons of real designers; Historical Perspectives, which provide a deeper look at computer design history; Putting it all Together, which present a design example that illustrates the principles of the chapter; Worked Examples, which challenge the reader to apply the concepts, theories and methods in smaller scale problems; and Cross-Cutting Issues, which show how the ideas covered in one chapter interact with those presented in others. In addition, a new feature, Another View, presents brief design examples in one of the three domains other than the one chosen for Putting It All Together.
The authors present a new organization of the material as well, reducing the overlap with their other text, Computer Organization and Design: A Hardware/Software Approach 2/e, and offering more in-depth treatment of advanced topics in multithreading, instruction level parallelism, VLIW architectures, memory hierarchies, storage devices and network technologies.
Also new to this edition, is the adoption of the MIPS 64 as the instruction set architecture. In addition to several online appendixes, two new appendixes will be printed in the book: one contains a complete review of the basic concepts of pipelining, the other provides solutions a selection of the exercises. Both will be invaluable to the student or professional learning on her own or in the classroom.
Hennessy and Patterson continue to focus on fundamental techniques for designing real machines and for maximizing their cost/performance.
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Foreword
Preface
Acknowledgments
Chapter 1 - Fundamentals of Computer Design
Chapter 2 - Instruction Set Principles and Examples
Chapter 3 - Instruction-Level Parallelism and Its Dynamic Exploitation
Chapter 4 - Exploiting Instruction-Level Parallelism with Software Approaches
Chapter 5 - Memory Hierarchy Design
Chapter 6 - Multiprocessors and Thread-Level Parallelism
Chapter 7 - Storage Systems
Chapter 8 - Interconnection Networks and Clusters
Appendix A - Pipelining: Basic and Intermediate Concepts
Appendix B - Solutions to Selected Exercises Online Appendices
Appendix C - A Survey of RISC Architectures for Desktop, Server, and Embedded Computers
Appendix D - An Alternative to RISC: The Intel 80x86
Appendix E - Another Alternative to RISC: The VAX Architecture
Appendix F - The IBM 360/370 Architecture for Mainframe Computers
Appendix G - Vector Processors Revised by Krste Asanovic
Appendix H - Computer Arithmetic by David Goldberg
Appendix I - Implementing Coherence Protocols
References
Index
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第四版简介:
本书堪称计算机系统结构学科的“圣经”，是计算机体系结构方向的学生的必读教材。全书系统地介绍了计算机系统的设计基础、指令集系统结构、流水线与指令级并行技术、层次化存储系统与存储设备、互连网络以及多处理器系统等重要内容。在这一最新版本中，作者更新了从单核处理器到多核处理器的历史发展过程的相关内容，同时使用了广受好评的“量化研究方法”进行计算设计，并阐述了多种可以实现并行的技术，这些技术恰恰是展现多处理器系统结构威力的关键。在介绍多处理器时，作者不仅讲述了处理器的性能，而且还介绍了处理器性能之外的其他设计要素，包括功耗、可靠性、可用性和可信性等。.
本书可作为计算机专业计算机系统结构方向的高年级本科生及研究生的教材，也可以作为相关技术人员的参考书。...
Computer Architecture
A Quantitative Approach
Fourth Edition
[codebox]
Features & Benefits | Reviews | Description | Contents
John Hennessy
Stanford University
David Patterson
University of California, Berkeley
Features & Benefits
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Increased coverage on achieving parallelism with multiprocessors.
Case studies of latest technology from industry including the Sun Niagara Multiprocessor, AMD Opteron, and Pentium 4.
Three review appendices, included in the printed volume, review the basic and intermediate principles the main text relies upon.
Eight reference appendices, collected on the CD, cover a range of topics including specific architectures, embedded systems, application specific processors--some guest authored by subject experts.
Reviews
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“If Neil Armstrong offers to give you a tour of the lunar module, or Tiger Woods asks you to go play golf with him, you should do it. When Hennessy and Patterson offer to lead you on a tour of where computer architecture is going, they call it Computer Architecture: A Quantitative Approach, 4th Edition. You need one. Tours leave on the hour.”
— Robert Colwell, Intel lead designer
“The book has been updated so it covers the latest computer architectures like the 64-bit AMD Opteron as well as those from Sun, Intel and other major vendors ... I highly recommend this book for those learning about computer architecture or those wanting to understand architectures that differ from those they are currently using. It does an excellent job of
covering most of the major architectural approaches employed today.”
— William Wong, Electronic Design, November 2006
“Computer hardware is entering into a new era, what with multicore processing, virtualization and other enhancements … Computer Architecture covers these topics and updates the insightful work in the earlier editions that laid out the full range of metrics needed for evaluating processor performance.”
— Joab Jackson, GCN, November 20, 2006
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The era of seemingly unlimited growth in processor performance is over: single chip architectures can no longer overcome the performance limitations imposed by the power they consume and the heat they generate. Today, Intel and other semiconductor firms are abandoning the single fast processor model in favor of multi-core microprocessors--chips that combine two or more processors in a single package. In the fourth edition of Computer Architecture, the authors focus on this historic shift, increasing their coverage of multiprocessors and exploring the most effective ways of achieving parallelism as the key to unlocking the power of multiple processor architectures. Additionally, the new edition has expanded and updated coverage of design topics beyond processor performance, including power, reliability, availability, and dependability.
CD System Requirements
PDF Viewer
The CD material includes PDF documents that you can read with a PDF viewer such as Adobe, Acrobat or Adobe Reader. Recent versions of Adobe Reader for some platforms are included on the CD.
HTML Browser
The navigation framework on this CD is delivered in HTML and javascript. It is recommended that you install the latest version of your favorite HTML browser to view this CD. The content has been verified under Windows XP with the following browsers: Internet Explorer 6.0, Firefox 1.5; under Mac OS X (Panther) with the following browsers: Internet Explorer 5.2, Firefox 1.0.6, Safari 1.3; and under Mandriva Linux 2006 with the following browsers: Firefox 1.0.6, Konqueror 3.4.2, Mozilla 1.7.11.
The content is designed to be viewed in a browser window that is at least 720 pixels wide. You may find the content does not display well if your display is not set to at least 1024x768 pixel resolution.
Operating System
This CD can be used under any operating system that includes an HTML browser and a PDF viewer. This includes Windows, Mac OS, and most Linux and Unix systems.
Contents back to top
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1 Fundamentals of Computer Design
1.1 Introduction
1.2 The Changing Face of Computing and the Task of the Computer Designer
1.3 Technology Trends
1.4 Power in Integrated Circuits
1.5 Trends in Cost
1.6 Reliability, Availability and Dependability
1.7 Measuring and Reporting Performance
1.8 Quantitative Principles of Computer Design
1.9 Putting It All Together: Performance and Price-Performance
1.10 Fallacies and Pitfalls
1.11 Concluding Remarks
2 Instruction Level Parallelism and Its Exploitation
2.1 Instruction-Level Parallelism: Concepts and Challenges
2.2 Basic Compiler Techniques for Exposing ILP
2.3 Reducing Branch Costs with Prediction
2.4 Overcoming Data Hazards with Dynamic Scheduling
2.5 Dynamic Scheduling: Examples and the Algorithm
2.6 Hardware-Based Speculation
2.7 Exploiting ILP using Multiple Issue and Static Scheduling
2.8 Exploiting ILP using Dynamic Scheduling, Multiple Issue, and Speculation
2.9 Advanced Techniques for Instruction Delivery and Speculation
2.10 Putting It All Together: The Intel Pentium 4
2.11 Fallacies and Pitfalls
2.12 Concluding Remarks
3 Advanced Techniques for Exploiting Instruction-Level Parallelism and Their Limits
3.1 Introduction
3.2 Studies of the Limitations of ILP
3.3 Limitations on ILP for Realizable Processors
3.4 Crosscutting Issues: Hardware versus Software Speculation
3.5 Multithreading: Using ILP Support to Exploit Thread-level Parallelism
3.6 Putting It All Together: Performance and Efficiency in
Advanced Multiple Issue Processors
3.7 Fallacies and Pitfalls
3.8 Concluding Remarks
4 Multiprocessors and Thread-Level Parallelism
4.1 Introduction
4.2 Symmetric Shared-Memory Architectures
4.3 Performance of Symmetric Shared-Memory Multiprocessors
4.4 Distributed Shared Memory and Directory-Based Coherence
4.5 Synchronization: The Basics
4.6 Models of Memory Consistency: An Introduction
4.7 Crosscutting Issues
4.8 Putting It All Together: The Sun T1 Multiprocessor
4.9 Fallacies and Pitfalls
4.10 Concluding Remarks
5 Memory Hierarchy Design
5.1 Introduction
5.2 Eleven Advanced Optimizations of Cache Performance
5.3 Memory Technology and Optimizations
5.4 Protection: Virtual Memory and Virtual Machines
5.5 Crosscutting Issues: The Design of Memory Hierarchies
5.6 Putting It All Together: AMD Opteron Memory Hierarchy
5.7 Fallacies and Pitfalls
5.8 Concluding Remarks
6 Storage Systems
6.1 Introduction
6.2 Advanced Topics in Disk Storage
6.3 Definition and Examples of Real Faults and Failures
6.4 I/O Performance, Reliability Measures, and Benchmarks
6.5 A Little Queuing Theory
6.6 Crosscutting Issues
6.7 Designing and Evaluating an I/O System - The Internet Archive Cluster
6.8 Putting It All Together: NetApp FAS6000 Filer
6.9 Fallacies and Pitfalls
6.10 Concluding Remarks
Appendix A: Pipelining: Basic and Intermediate Concepts
A.1 Introduction
A.2 The Major Hurdle of Pipelining—Pipeline Hazards
A.3 How Is Pipelining Implemented?
A.4 What Makes Pipelining Hard to Implement?
A.5 Extending the MIPS Pipeline to Handle Multicycle Operations
A.6 Putting It All Together: The MIPS R4000 Pipeline
A.7 Crosscutting Issues
A.8 Fallacies and Pitfalls
A.9 Concluding Remarks
Appendix B: Instruction Set Principles and Examples
B.1 Introduction
B.2 Classifying Instruction Set Architectures
B.3 Memory Addressing
B.4 Addressing Modes for Signal Processing 1
B.5 Type and Size of Operands
B.6 Operations in the Instruction Set
B.7 Instructions for Control Flow
B.8 Encoding an Instruction Set
B.9 Crosscutting Issues: The Role of Compilers
B.10 Putting It All Together: The MIPS Architecture
B.11 Fallacies and Pitfalls
B.12 Concluding Remarks
Appendix C: Introduction to Memory Hierarchy
C.1 Introduction
C.2 Cache Performance
C.3 Seven Basic Cache Optimizations
C.4 Virtual Memory
C.5 Protection and Examples of Virtual Memory
C.6 Fallacies and Pitfalls
C.7 Concluding Remarks
